Publications

Book & Book Chapter

  1. S.M.Nabavi Nejad, M. Goudarzi, Chapter 5: Communication-Awareness for Energy-Efficiency in Datacenters, pp. 201-254, A. Hurson & H. Sarbazi Azad Eds., Advances in Computers, Vol. 100, Elsevier Inc. Academic Press, Burlington, USA, 2016.
  2. M. Goudarzi, S. Hessabi, ESL Design of Object-Oriented Applications: The ODYSSEY Approach, Nova Science Publishers, New York, March 2012.

 

Journal papers

  1. M. Goudarzi, “Architectures for Big Data Batch Processing in MapReduce Paradigm,” IEEE Trans. Big Data, in press, July 2017.
  2. S.M. Nabavi Nejad, M. Goudarzi, “Faster MapReduce Computation on Clouds through Better Performance Estimation,” IEEE Trans. Cloud Computing, in press, Feb. 2017.
  3. H. Ahmadvand, M. Goudarzi, “Using Data Variety for Efficient Progressive Big Data Processing in Warehouse-Scale Computers,” IEEE Computer Architecture Letters, in press, Nov. 2016.
  4. S.M. Nabavi Nejad, M. Goudarzi, Sh. Mozaffari “The Memory Challenge in Reduce Phase of MapReduce Applications,” IEEE Trans. Big Data, in press, Sep. 2016 (online access).
  5. A. Varasteh, M. Goudarzi, “Server Consolidation Techniques in Virtualized Data Centers: A Survey,” IEEE Systems Journal, in press, July 2015 (online access).
  6. S. Taheri, M. Goudarzi, “Reducing Break-Even Time by Smart Power Management in Data Centers with Renewable Energy,” Int’l Journal of Information Technology Management, University of Tehran, in press, July 2015 (in Persian).
  7. V. Ebrahimi Rad, M. Goudarzi, A. Rajabi, “Energy-Aware Scheduling for Precedence-Constrained Parallel Virtual Machines in Virtualized Data Centers,” Springer Journal of Grid Computing, Feb. 2015 (online access).
  8. M. Khavari Tavana, S. Ahmadian, M. Goudarzi, “Dynamically Adaptive Register File Architecture for Energy Reduction in Embedded Processors,” Elsevier Microprocessors and Microsystems, in press, Jan. 2015 (online access).
  9. M. Momtazpour, Omid Assare, Negar Rahmati, Amirali Boroumand, Saeid Barati, M. Goudarzi, “Yield-Driven Design-Time Task Scheduling Techniques for MPSoCs under Process Variation: A Comparative Study,” IET Journal of Computers & Digital Techniques, in press, Dec. 2014.
  10. H. Javidi, M. Goudarzi, “TABEMS: Tariff-Aware Building Energy Management System for Sustainability through Better Use of Electricity,” The Computer Journal, Oxford University Press, in press, Oct. 2014 (online access).
  11. S. Esfandiarpour, A. Pahlavan, M. Goudarzi, “Structure-Aware Online Virtual Machine Consolidation for Datacenter Energy Improvement in Cloud Computing,” Elsevier Journal of Computers and Electrical Engineering, in press, Sep. 2014 (online access).
  12. M. Zare, S. Hessabi, M. Goudarzi, “A Heuristic Algorithm for Periodic Clock Optimization in Scheduling Based Latency-Insensitive Design,” IET Journal of Computers & Digital Techniques, in press, Sep. 2014.
  13. A. Pahlavan, M. Momtazpour, M. Goudarzi, “Power Reduction in HPC Data Centers: A Joint Server Placement and Chassis Consolidation Approach,” Springer Journal of Supercomputing, in press, July 2014 (online access).
  14. M. Khavari Tavana, N. Teimouri, M. Abdollahi, M. Goudarzi, “Simultaneous Hardware and Time Redundancy with Online Task Scheduling for Low Energy Highly Reliable Standby-Sparing System,” ACM Trans. on Embedded Computing Systems, , Feb. 2014 (online access).
  15. O. Assare, M. Momtazpour, M. Goudarzi, “Leak-Gauge: A Late-Mode Variability-Aware Leakage Power Estimation Framework,” Elsevier Journal of Microprocessors and Microsystems, Nov. 2013 (online access).
  16. M. Zare, S. Hessabi, M. Goudarzi, “An Efficient Synchronization Circuit in Multi-Rate SDH Networks,” Journal of AJSE, in press, Jan. 2013.
  17. M. Zare, S. Hessabi, M. Goudarzi, “Throughput Enhancement for Repetitive Internal Cores in Latency-Insensitive Systems,” IET Journal of Computers & Digital Techniques, September 2012 (online access).
  18. M. Momtazpour, M. Goudarzi, E. Sanaei, “Static Statistical MPSoC Power Optimization by Variation-Aware Task and Communication Scheduling,” Elsevier Journal of Microprocessors and Microsystems, in press, Feb. 2012 (online access).
  19. M. Goudarzi, T. Ishihara, H. Noori, “Software-Level Instruction-Cache Leakage Reduction using Value-Dependence of SRAM Leakage in Nanometer Technologies,” Transactions on High-Performance Embedded Architectures and Compilers III, LNCS Vol. 6590, pp. 275-299, 2011 (online access).
  20. M. Momtazpour, M. Goudarzi, E. Sanaei, “Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization,” IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences (Special Section on “VLSI Design and CAD Algorithms”), E93-A(12), pp. 2542-2550, Dec. 2010 (online access).

 

Conference papers

  1. S. Nasehi, A. Divband, M. Goudarzi, “Processing- and Communication-Aware Data Partitioning for Efficient Execution of MapReduce Jobs (in Persian),” 22nd Computer Society of Iran Computer Conference (CSICC’95), Tehran, Iran, Mar. 2017
  2. H. Nasiri, M. Goudarzi, “Dynamic FPGA-Accelerator Sharing among Concurrently Running Virtual Machines,” 14th IEEE East-West Design & Test Symposium (EWDTS’16), Yerevan, Armenia, in press, Oct. 2016.
  3. S.M. Nabavi Nejad, M. Goudarzi, “Energy Efficiency in Cloud-Based MapReduce Applications through Better Performance Estimation,” Design, Automation and Test in Europe (DATE’16), Dresden, Germany, in press, Mar. 2016.
  4. M. Biglari, K. Mirzazad, M. Goudarzi, B. Pourmohseni, “A Fine-Grained Configurable Cache Architecture for Soft Processors,” Int’l Conf. on Computer Architecture and Digital Systems (CADS’15), Tehran, Iran, in press, Oct. 2015.
  5. B. Ranjbar, S. Taheri, M. Goudarzi, “Energy-Aware Scheduling of Service jobs in Data Centers with Renewable Energy and Distributed UPS,” Iranian Conf. on Electrical Engineering (ICCE’14), Tehran, Iran, May 2014 (in Persian).
  6. V. Ebrahimi Rad, A. Rajabi, M. Goudarzi, “Energy-aware Scheduling Algorithm for Precedence-Constrained Parallel Tasks of Network-intensive Applications in a Distributed Homogeneous Environment,” Int’l eConf. on Computer and Knowledge Engineering (ICCKE’13), Mashad, Iran, Nov. 2013.
  7. E. Azimzadeh, M. Sameki, M. Goudarzi, “Performance Analysis of Android Underlying Virtual Machine in Mobile Phones,” IEEE International Conference on Consumer Electronics (ICCE), Berlin, Germany, Sep 2012.
  8. O. Assare, M. Momtazpour, M. Goudarzi, “Accurate Estimation of Leakage Power Variability in Sub-Micrometer CMOS Circuits,” The 15th Euromicro Conference on Digital System Design (Euro-DSD), Izmir, Turkey, Sep 2012. Best Paper Award Candidate.
  9. A. Pahlavan, M. Momtazpour, M. Goudarzi, “Variation-Aware Server Placement and Task Assignment for Data Center Power Minimization,” The 10th IEEE Int’l Symp. on Parallel and Distributed Processing with Applications (ISPA), Madrid, Spain, July 2012.
  10. A. Pahlavan, M. Momtazpour, M. Goudarzi, “Data Center Power Reduction by Heuristic Variation-Aware Server Placement and Chassis Consolidation,” The 16th CSI Int’l Symp. on Computer Architecture and Digital Systems (CADS), Shiraz, Iran, May 2012.
  11. O. Assare, H. Izady Rad, M. Momtazpour, E. Sanaei, M. Goudarzi, “VAREX: A Post-P&R Variability Modeling Framework for Multiprocessor SoCs,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), in conjuction with ICCAD conf., San Jose, CA, Nov. 2011.
  12. M. Zare, S. Hessabi, M. Goudarzi, “Efficient Periodic Clock Calculus in Latency-Insensitive Design,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, Dec. 2011.
  13. O. Assare, M. Goudarzi, “Opportunities for Embedded Software Power Reductions,” IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Niagara Falls, Canada, May 2011.
  14. M. Momtazpour, M. Ghorbani, M. Goudarzi, E. Sanaei, “Simultaneous Variation-Aware Architecture Exploration and Task Scheduling for MPSoC Energy Minimization,” Great Lakes Symposium on VLSI (GLSVLSI), Switzerland, May 2011.
  15. M. Ghorbani, M. Momtazpour, M. Goudarzi, “Energy-Aware Simultaneous Architecture Exploration and Task Scheduling for MPSoCs under Process Variation,” Workshop on Micro Power Management for Macro Systems on Chip (uPM2SoC) in conjuction with DATE conference, Poster presentation, Grenoble, France, Mar. 2011.
  16. M. Momtazpour, E. Sanaei, M. Goudarzi, “Variation-Aware Task Scheduling for MPSoC Power-Yield Optimization,” PhD Forum of Int’l Conf. on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, Sep. 2010.
  17. M. Momtazpour, M. Goudarzi, E. Sanaei, “Variation-Aware Task Scheduling and Power Mode Selection for MPSoC Power Optimization,” CSI Int’l Symposium on Computer Architecture and Digital Systems (CADS), pp. 33-39, Tehran, Iran, Sep. 2010.
  18. M. Momtazpour, E. Sanaei, M. Goudarzi, “Power-Yield optimization in MPSoC Task Scheduling under Process Variation,” Int’l Symposium on Quality Electronic Design (ISQED), pp. 747-754, San Jose, CA, Mar. 2010.

 

Further Prior Publications of the Lab Director

 

Journals

  1. M. Goudarzi, T. Ishihara, “SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-die Delay Variation,” IEEE Trans. VLSI, 18(12), pp. 1660-1671, Dec. 2010 (online access).
  2. M. Goudarzi, T. Ishihara, H. Yasuura, “A Software Technique to Improve Lifetime of Caches Containing Ultra-Leaky SRAM Cells Caused by Within-Die Vth Variation,” Elsevier Journal of Microelectronics, 39(12), Dec. 2008 (online access).
  3. M. Goudarzi, T. Matsumura, T. Ishihara, “Way-Scaling to Reduce Power of Cache with Delay Variation,” IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences (Special Section on “VLSI Design and CAD Algorithms”), E91-A(12), Dec. 2008.
  4. M. Goudarzi, S. Hessabi, N. MohammadZadeh, N. Zeinolabedini, “The ODYSSEY Approach to Early Simulation-based Equivalence-Checking at ESL Level using Automatically-Generated Executable Transaction-Level Model,” Elsevier Journal of Microprocessors & Microsystems (now J. Embedded Hardware Design), 32(7), Oct. 2008 (online access).
  5. M. Goudarzi, T. Ishihara, “Process-Variation-Aware Instruction Rescheduling to Reduce Leakage in Nanometer Instruction Caches,” CSI (Computer Society of Iran) Journal on Computer Science and Engineering, in press, 2008.
  6. N. MohammadZadeh, S. Hessabi, M. Goudarzi, M. Malaki, “A Framework for Object-Oriented Embedded System Development Based on OO-ASIPS,” Journal of Circuits, Systems, and Computers, World Scientific, vol. 17, no. 6, pp. 973-993, Dec. 2008. (online version)
  7. H. Noori, M. Goudarzi, K. Inoue, K. Murakami, “Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems,” IEICE Transactions on Electronics (Special Section: Advanced Technologies in Digital LSIs and Memories), E91-C(4), Apr. 2008 (online access).
  8. M. Goudarzi, T. Ishihara, “Value-Dependence of SRAM Leakage in Deca-Nanometer Technologies,” IEICE Electronics Express (ELEX), Jan. 2008 (online access).
  9. M. Goudarzi, N. MohammadZadeh, S. Hessabi, “Using On-Chip Networks to Implement Polymorphism in the Co-design of Object-Oriented Embedded Systems,” Elsevier Journal of Computer and System Sciences (JCSS), Special Issue on Network-Based Computing, Dec. 2007 (online access).
  10. A.M. Gharehbaghi, S. Hessabi, B. Hamdin Yaran, M. Goudarzi, “An Assertion-Based Verification Methodology for System-Level Design,” Elsevier Journal of Computers and Electrical Engineering, July 2007 (online access)
  11. M. Goudarzi, S. Hessabi, A. Mycroft, “Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs,” Journal of Universal Computer Science, vol. 10, no. 9, pp. 1123-1155, Sep. 2004 (onlne access).

 

 Conference Papers

  1. D. Vasudevan, M. Goudarzi, E. Popovici, M. Schellekens, “A Reversible MIPS Multi-cycle Control FSM Design,” Asia Symposium on Quality Electronic Design (ASQED), Kualalumpur, Malaysia, July 2009.
  2. M. Goudarzi, J. Chen, D. Vasudevan, E. Popovici, M. Schellekens, “Reversing Deterministic Finite State Machines,” 20th Irish Signals and Systems Conference (ISSC), Dublin, June 2009.
  3. M. Goudarzi, T. Ishihara, “Row/Column Redundancy to Reduce SRAM Leakage in Presence of Within-Die Delay Variation,” Int’l Symp. on Low Power Elec. & Design (ISLPED’08), Bangalore, India, Aug. 2008.
  4. M. Goudarzi, T. Ishihara, “Instruction Cache Leakage Reduction by Changing Register Operands and Using Asymmetric SRAM Cells,” Great Lakes Symp. on VLSI (GLSVLSI’08), Orlando, May 2008.
  5. M. Goudarzi, T. Matsumura, T. Ishihara, “Cache Power Reduction in Presence of Within-Die Delay Variation using Spare Ways,” IEEE Annual Symp. on VLSI (ISVLSI’08), Montpellier, France, Apr. 2008.
  6. H. Noori, M. Goudarzi, K. Inoue, K. Murakami, “Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection,” IEEE Annual Symp. on VLSI (ISVLSI), Montpellier, France, Apr. 2008.
  7. M. Goudarzi, T. Ishihara, H. Noori, “Variation-Aware Software Techniques for Cache Leakage Reduction using Value-Dependence of SRAM Leakage due to Within-Die Process Variation,” Int’l Conf. on High Performance Embedded Architectures & Compilers (HiPEAC’08), LNCS 4917, pp. 224-239, Goteborg, Sweden, Jan. 2008.
  8. H. Noori, F. Mehdipour, M. Goudarzi, S. Yamaguchi, K. Inoue, and K. Murakami, “Energy Consumption Evaluation of an Adaptive Extensible Processor,”Proc. of Reconfigurable and Adaptive Architecture Workshop (RAAW) in conjunction with IEEE/ACM International Symposium on Microarchitecture, Dec. 2007.
  9. M. Goudarzi, T. Matsumura, T. Ishihara, “Taking Advantage of Within-Die Delay-Variation to Reduce Cache Leakage Power Using Additional Cache-Ways,” Proc. of Int’l Workshop on Dependable Embedded Systems (WDES’07) in conjunction with 26th Symposium on Reliable Distributed Systems (SRDS 2007), Beijing, China, Oct. 2007.
  10. T. Matsumura, Y. Ishitobi, M. Goudarzi, T. Ishihara, Hiroto Yasuura, “A Hybrid Memory Architecture for Low Power On-Chip Memory Design,” Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI’07), Hokkaido, Japan, Oct. 2007.
  11. H. Noori, M. Goudarzi, K. Inoue, and K. Murakami, “The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems,” Proc. of Int’l Conf. on Embedded Systems and Applications (ESA’07), June 2007.
  12. H. Noori, F. Mehdipour, K. Murakami, K. Inoue, M. Goudarzi, “Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor,” Proc. of Design-Automation and Test in Europe (DATE’07), Mar. 2007.
  13. N. MohammadZadeh, M. NajafVand, S. Hessabi, M. Goudarzi, “Implementation of a JPEG Object-Oriented ASIP: A Case Study on a System-Level Design Methodology,” Proc. of Great Lakes Symposium on VLSI (GLSVLSI’07), Mar. 2007.
  14. H. Noori, M. Goudarzi, K. Inoue, K. Murakami, “The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems,” Proc. of Great Lakes Symposium on VLSI (GLSVLSI’07), Mar. 2007.
  15. M. Goudarzi, T. Ishihara, H. Yasuura, “Ultra-Leaky SRAM Cells Caused by Process Variation: Detection and Leakage Suppression at System-Level,” Proc. of Computer Society of Iran Computer Conference (CSICC’07), Tehran, Feb. 2007.
  16. M. Goudarzi, T. Ishihara, H. Yasuura, “A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation,” Proc. of Asia and South-Pacific Design Automation Conference (ASP-DAC’07), Japan, Jan. 2007.
  17. S. Hessabi, M. Modarressi, M. Goudarzi, H. Javanhemmat “A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems,” Proc. of IEEE IC-SAMOS conference, Greece, July 2006.
  18. H. JavanHemmat, M. Goudarzi, S. Hessabi, “On the Hardware-Software Partitioning: The Classic General Model (CGM),” Proc. of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE’06), Canada, May 2006.
  19. M. Modarressi, S. Hessabi, M. Goudarzi, “A Reconfigurable Cache Architecture for Object-Oriented Application-Specific Processors,” Proc. of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE’06) , Canada, May 2006.
  20. N. Mohammadzadeh, S. Hessabi, M. Goudarzi, “Evolving an MPEG2 Processor from a JPEG Object-Oriented ASIP: A Case Study on a System-Level Design Methodology,” Proc. of Computer Society of Iran Computer Conference (CSICC’06), 2006.
  21. M. Modarressi, H. JavanHemmat, M. Najafvand, M. Goudarzi, S. Hessabi, “A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing,” Proc. of Computer Society of Iran Computer Conference (CSICC’06), 2006.
  22. M. Modarressi, S. Hessabi, M. Goudarzi, “A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling,” in Proc. of The Third IEEE Workshop on Electronic Design, Test, and Applications (DELTA’06), Malaysia, Jan. 2006.
  23. N. MohammadZadeh, S. Hessabi, M. Goudarzi, “Software Implementation of MPEG2 Decoder on an ASIP JPEG Processor,” Proc. of IEEE International Conference on Microelectronics (ICM’05), Islamabad, Pakistan, Dec. 2005.
  24. M. Modarressi, M. Goudarzi, S. Hessabi, “Application-Specific Hardware-Driven Prefetching To Improve Data Cache Performance,” in Tenth Asia-Pacific Computer System Architecture Conference (ACSAC’05), Singapore, LNCS 3740, pp. 761-774, Oct. 2005.
  25. M. Goudarzi, S. Hessabi, “The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models,” in SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Greece, Springer-Verlag LNCS 3553, pp. 394-403, July 2005.
  26. S. Hessabi, A.M. Gharehbaghi, B. Hamdin Yaran, M. Goudarzi, “Integrating Assertion-Based Verification into System-Level Synthesis Methodology,” Proc. of IEEE International Conference on Microelectronics (ICM’04), Tunisia, Dec. 2004.
  27. M. Goudarzi, S. Hessabi, A. Mycroft, “Object-aware Cache: Higher Cache Hit-ratio in Object-Oriented ASIPs,” Proc. of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE’04), Ontario, Canada, May 2004.
  28. M. Goudarzi, S. Hessabi, A. Mycroft, “No-Overhead Polymorphism in Network-on-Chip Implementation of Object-Oriented Models,” Proc. of IEEE/ACM Design Automation and Test in Europe (DATE’04), Paris, Feb. 2004.
  29. M. Goudarzi, S. Hessabi, “Synthesis of Object-Oriented Descriptions Modeled at Functional-Level,” Proc. of International Conference on Electronics, Control and Signal processing (ICECS’03), Singapore, Dec. 2003.
  30. M. Goudarzi, S. Hessabi, A. Mycroft, “Object-oriented ASIP Design and Synthesis,” Proc. of Forum on specification and Design Languages (FDL’03), Sep. 2003.
  31. M. HashemPour, S. Sharifi, M. Gudarzi, S. Hessabi, “Rapid Design Space Exploration of DSP Applications Using Programmable SoC Devices – A Case Study,” Proc. of 15th IEEE int’l ASIC/SoC Conference, NY, USA, Sep. 2002.
  32. S. Hessabi, A. Ahmadinia, G. Asadi, S. Bayat Sarmadi, M. Gudarzi, “Co-FFT Design: FFT Implementation on CSoC,” IEEE-TTTC int’l conf. on Automation, Quality and Testing, Robotics (A&QT-R 2002), Cluj-Napoca, Romania, May 2002.
  33. O.F. NadjarBashi, M. Gudarzi, S. Hessabi, “DCT-2D Co-Module: An Implementation of Discrete Cosine Transform Using SoC Approach,” Proc. of 7th Annual Computer Society of Iran Conference, Tehran, Iran, Feb. 2002.
  34. M. Jamzad, M. Gudarzi, et al, “A Goal Keeper for Middle Size RoboCup,” RoboCup-2000: Robot Soccer World Cup IV, P. Stone, T. Balch, and G. Kraetszchmar (eds.), Lecture Notes in Artificial Intelligence (LNAI) 2019, Springer-Verlag, Berlin, pp. 583-586, 2001.
  35. M. Gudarzi, S. Hessabi, “Built-In Self-Test of FPGA Logic Blocks with no Area/Delay Overhead,” Proc. of The 4th Int’l Computer Society of Iran Conference, Tehran, Iran, Jan. 1999 (in Persian).